SCT2650

本文介绍一款DCDC的芯片，SCT2650STER：4.5V-60V Vin, 5A，高效率降压DCDC转换器，可编程频率(4.5V-60V Vin, 5A, High Efficiency Step-down DCDC Converter with Programmable Frequency)

规格书摘要

产品特点

• Wide Input Range: 4.5V-60V
• Up to 5A Continuous Output Current
• 0.8V ±1% Feedback Reference Voltage
• Adjustable Frequency 100KHz to 1.2MHz

大致的电气特性

3.3V参考设计：

PIN Function

Switching Frequency

输出电压

500KHz典型输出电压参考表

规格书中还提到有逆变器方面的应用(Inverting Power application)

这颗IC在24V输入3.3V输出5A电流时，温度高达92°C

在IC下方有一个大面积阻焊层连接到IC目的就是更好地散热

Layout 设计参考

线上图

Proper PCB layout is a critical for SCT2650’s stable and efficient operation. The traces conducting fast switching currents or voltages are easy to interact with stray inductance and parasitic capacitance to generate noise and degrade performance. For better results, follow these guidelines as below:

1. Power grounding scheme is very critical because of carrying power, thermal, and glitch/bouncing noise associated with clock frequency. The thumb of rule is to make ground trace lowest impendence and power are distributed evenly on PCB. Sufficiently placing ground area will optimize thermal and not causing over heat area.
2. Place a low ESR ceramic capacitor as close to VIN pin and the ground as possible to reduce parasitic effect.
3. Freewheeling diode should be place as close to SW pin and the ground as possible to reduce parasitic effect.
4. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. Make sure top switching loop with power have lower impendence of grounding.
5. The bottom layer is a large ground plane connected to the ground plane on top layer by vias. The power pad should be connected to bottom PCB ground planes using multiple vias directly under the IC. The center thermal pad should always be soldered to the board for mechanical strength and reliability, using multiple thermal vias underneath the thermal pad. Improper soldering thermal pad to ground plate on PCB will cause SW higher ringing and overshoot besides downgrading thermal performance. it is recommended 8mil diameter drill holes of thermal vias, but a smaller via offers less risk of solder volume loss. On applications where solder volume loss thru the vias is of concern, plugging or tenting can be used to achieve a repeatable process.
6. Output inductor and freewheeling diode should be placed close to the SW pin. The switching area of the PCB conductor minimized to prevent excessive capacitive coupling.
7. The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace.
8. UVLO adjust and RT resistors, loop compensation and feedback components should connect to small signal ground which must return to the GND pin without any interleaving with power ground.
9. Route BOOT capacitor trace on the other layer than top layer to provide wide path for topside ground.
10. For achieving better thermal performance, a four-layer layout is strongly recommended.

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Layout 设计

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